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Several years of work experience debugging RTL at the block and/or top-level Hands-on verification utilizing System Verilog/UVM Architecting/creating RTL testbenches from scratch IP knowledge include Serdes, PCIe, ARM Subsystem, DSPs/Accelerators, or Ethernet TCL/Python/Perl/etc.
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O Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness. o Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
ExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP. Expert-level knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C.
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Experience in creating, running and debugging of System Verilog/UVM constraint-random Testbench. Develop Scalable System Verilog/UVM testbenches for unit level and/or Cluster level verification.
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Knowledge about UVM methodology and C-DPI methodology Excellent knowledge about standard bus/interface protocols (i.e. AXI, AHB, AMBA) Excellent experience with firmware design on commercial microprocessors Excellent experience with microprocessor tool chain, compiler, assembler, debugger Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc.
Full-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Industry experience developing testbenches and verification components with SystemVerilog and UVM. Experience using MATLAB or other high-level modeling language/tool. Architect and implement testbenches and verification components using UVM-based methods.
ExpandApply NowActive JobUpdated 4 days ago - UpvoteDownvoteShare Job
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Identify design features for verification and functional coverage within verification tools such as System Verilog, UVM, and Verdi, among others. Develop and maintain System Verilog/UVM test benches.
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Object Oriented Programming, UVM, System Verilog. NVIDIA is seeking best-in-class Senior SoC ASIC Verification Engineer to verify the world's most powerful SoCs with AI capabilities for self-driving cars, gaming consoles & other automated machines (see NVIDIA Grace CPU and Arm Architecture | NVIDIA.
$156,000 - $287,500 a yearFull-timeExpandApply NowActive JobUpdated 3 months ago - UpvoteDownvoteShare Job
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Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment. Architect UVM-based highly reusable test benches and integrate sophisticated multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, and work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design.
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The Austin Digital IP team develops components for DDR, Ethernet, high-speed serial links, cores, caches, and interconnect Job Summary: Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications) Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
ExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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PREFERRED EXPERIENCE: Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench. THE ROLE: The Memory IO team is looking for passionate and experienced Verification engineers for the verification of high-speed LPDDRx, DDRx and associated IPs through the utilization of complex co-simulation hybrid environments and traditional UVM methodologies.
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Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Verify complex design blocks using equally complex SV/UVM verification environments.
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The position requires a thorough UVM development and deployment background with a focus on DSP and Wireless blocks. Industry experience developing testbenches and verification components with SystemVerilog and UVM is required.
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Working knowledge of System Verilog and/or UVM. For example, the candidate may participate in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and/or full-chip mixed-signal verification.
$22.5 - $47.5 an hourFull-timeExpandApply NowActive JobUpdated 3 months ago - UpvoteDownvoteShare Job
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Designing and Deploying UVM and C-based AMS verification benches from scratch; Taking ownership of mixed-signal IP verification from specification to integration; Executing mixed-mode simulations with AMS blocks at SoC and Sub-system level; Debugging low-power designs with UPF; Ensuring that new IoT SoCs can deliver flawless performance.
$150,000 - $250,000 a year (bonuses)Full-timeExpandApply NowActive JobUpdated Today
uvm job in Austin, TX
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