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Senior Design Verification Engineer - Memory Subsystem Verification, C, System Verilog
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Full-time
- Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.
- SystemVerilog, UVM object-oriented design as well as scripting language.
- Experience in ground up development and verification using UVM/SystemVerilog with IP and Subsystem verification as main objective using VCS. Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification.
- PREFERRED EXPERIENCE: Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench.
- Zebu Emulation verification and debug experience.
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