Upvote
Downvote
Senior / Principal IP Verification Engineer
Share Job
- Suggest Revision
- Job Description Design Verification Engineer Business Line Description: MCU/MPU Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking.
- The Austin Digital IP team develops components for DDR, Ethernet, high-speed serial links, cores, caches, and interconnect Job Summary: Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications) Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
- Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan.
- Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness.
- Debugging failing testcases to determine source of failure (tool, testcase, checker, verilog RTL) and track resolution Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage.
Active Job
Updated TodaySimilar Job
Relevance
Active