Apple

As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs!. Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.. In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification.. Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes.. Architect UVM-based highly reusable test benches and integrate sophisticated multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, and work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design.

design verification engineer

Do you have a passion for invention and self-challenge? This position allows you to be a part of one of the most innovative and key projects that Apple's Silicon Engineering Group has embarked upon to date.
As part of our team, you will have the opportunity to take the lead and contribute to verifying a set of sophisticated SOCs. This team will allow you to integrate multiple sophisticated IP-level DV environments, craft highly reusable outstanding UVM TB, implement effective coverage-driven and directed test cases, deploy new tools, and implement methodologies to improve the quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large-scale SOC, different types of SOC architecture, many high-speed layered protocols, the industry's standard methodologies on low-power architecture, outstanding DV methodology, verification on accelerated platforms, knowledge of Cellular protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc.
As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs! This position requires someone comfortable will all areas of SoC design verification engineering. Someone who thrives in a dynamic multi-functional organization, someone who is not afraid to debate ideas openly, and is flexible enough to shift inconstantly evolving requirements.
Key Qualifications
<ul>
<li>Dedicated/hands-on ASIC DV experience.</li>
<li>Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM.</li>
<li>Proven record of working full ASIC cycle from concept to tape-out to bring-up.</li>
<li>Experience taping out large SOC systems with embedded processor cores.</li>
<li>Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.</li>
<li>In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification.</li>
<li>Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.</li>
<li>BS and a minimum of 3 years of relevant industry experience is required.</li>
</ul>
Description
Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes. Build coverage-driven verification plans from specifications, and review and refine them to achieve coverage targets. Create IP level module and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure. Architect UVM-based highly reusable test benches and integrate sophisticated multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, and work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design. Work closely with DV methodology architects to improve verification flow.
Education & Experience
BS and a minimum of 3 years of relevant industry experience is required. MSEE or beyond is preferred.

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