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Background with System Verilog and UVM based methodology for ASIC verification. 5 years of hands-on ASIC verification of challenging design units over multiple projects displaying good attention to detail, teamwork, problem solving and proven success Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6}) Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB.
$128,000 - $258,750 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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The primary skills required for this job are RTL design, simulation, expertise in mapping designs to emulation, improving model performance, excellent communication skills, and ability to work in a fast-paced exciting environment.
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Background with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA) Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies.
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Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or in any STEM related field of study with 1+ years of experience in Design Verification Developing UVM and/or Formal-based verification architectures and methodologies.
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Verification lead experience for multiple IP or SS related to Central Processing Unit (CPU), Vector Processing Unit (VPU), Graphics Processing Unit (GPU), Direct Memory Access (DMA) engine, Tensor unit (TU), or similar.
$158,500 - $276,600 a yearFull-timeExpandApply NowActive JobUpdated 10 days ago - UpvoteDownvoteShare Job
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In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification. Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
$138,900 - $256,500 a yearExpandUpdated Today - UpvoteDownvoteShare Job
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Proficient in System Verilog assertions and verification using UVM experience. GLS verification knowledge. We are looking for Senior Design Verification Engineer. Position - Senior Design Verification Engineer.
$88,800 - $187,740 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SoCs.
$170,700 - $256,500 a yearExpandUpdated Today - UpvoteDownvoteShare Job
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Advanced knowledge of ASIC verification flows with SystemVerilog and UVM. In this role you, will be responsible for ASIC pre-silicon verification of extremely complex high throughput communication PHY and Radio sub-systems.
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Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon. CPU Unit Verification Engineer will focus on the Unit/Block level verification for high-performance CPUs. The person coming into this role will help execute the verification strategy and the DV plan.
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Are you a senior or lead level CPU Architectural Design Verification Engineer looking to invent the future for performance computing in an energy challenged world? 5+ years' experience with complex software projects, including design verification methodology, random test generator development or instruction set simulator design.
$170,000 - $284,000 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus. Senior Design Verification Engineer. Familiarity with assertion writing and formal verification is a plus.
Full-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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The ideal candidate will have a robust background in ASIC design and verification, with a strong proficiency in SystemVerilog and UVM methodologies. 8+ years of experience in ASIC design, verification, or a related field.
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Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components.
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Experience or knowledge in clock domain crossing verification, power-aware verification, and development of complex SOCs on emulation platforms. Experience with SystemVerilog and verification methodologies (UVM/OVM.
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Title: insurance verification Company: Insight Choices in Mountain View, CA
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