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Background with System Verilog and UVM based methodology for ASIC verification. 5 years of hands-on ASIC verification of challenging design units over multiple projects displaying good attention to detail, teamwork, problem solving and proven success Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6}) Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB.
$128,000 - $258,750 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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SystemVerilog UVM and ASIC verification. Analog Mixed Signal Design Verification Engineer. Synapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position.
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Lumotive is seeking a Lead ASIC verification engineer to lead the verification of Beam Steering Mixed signal ASIC controller. Strong experience in chip/top level verification of complex Mixed Signal SoCs & ASIC.
$180,000 - $220,000Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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They are looking for a Senior/Principal ASIC Design Verification Engineer who is an expert with PCIe and CXL to help them accelerate AI cloud computing. As a Design Verification Engineer with this company you will work with test bench development using System Verilog and UVM as well as develop comprehensive test plans and cases with functional coverage, assertions, and coverage properties.
$220,000 - $250,000 a yearFull-timeExpandApply NowActive JobUpdated 8 days ago - UpvoteDownvoteShare Job
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Background with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA) Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies.
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Review specifications, extract features, define and execute verification plan in coordination with architects and analog designers -Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.
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Role: Mixed Signal Verification Engineer. Mixed Signal Verification Engineer. Expertise in developing and modifying UVM based environment for mixed signal including Verilog-AMS and wreal.
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Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or in any STEM related field of study with 1+ years of experience in Design Verification Developing UVM and/or Formal-based verification architectures and methodologies.
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Analog/Mixed-Signal Verification Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Analog/Mixed-Signal IC Verification Engineer. Experience with scan chain vector generation and verification.
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Verification lead experience for multiple IP or SS related to Central Processing Unit (CPU), Vector Processing Unit (VPU), Graphics Processing Unit (GPU), Direct Memory Access (DMA) engine, Tensor unit (TU), or similar.
$158,500 - $276,600 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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We are seeking individuals with experience in chip design, IP and SoC verification, emulation or prototyping, building verification environments with SystemVerilog/UVM/SystemC, developing and debugging testcases and with strong verbal and written communication skills in addition to excellent problem solving skills.
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In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification. Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
$170,700 - $256,500 a yearExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Advanced knowledge of ASIC verification flows with SystemVerilog and UVM. In this role you, will be responsible for ASIC pre-silicon verification of extremely complex high throughput communication PHY and Radio sub-systems.
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Fluent in writing protocols, compiling, Hardware verification, and firmware. Experience with scripting languages Low power experience (e.g., UPF) Formal verification experience and debugging.
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At European Recruitment we are working alongside a widely successful Bosch, Continental and BMW backed startup with locations in the US and Europe to help them bring on board a senior ASIC verification engineer.
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Title: insurance verification Company: Insight Choices in Santa Clara, CA
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