Microsoft

Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.. We are looking for a Principal Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team.. Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.. 10+ years of experience debugging Register Transfer Level (RTL) designs in simulation and emulation environments. Verification lead experience for multiple IP or SS related to Central Processing Unit (CPU), Vector Processing Unit (VPU), Graphics Processing Unit (GPU), Direct Memory Access (DMA) engine, Tensor unit (TU), or similar

design verification engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Principal Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
Responsibilities
Lead a pre-silicon verification team for the development of custom Intellectual Property (IP) and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features.
Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or SS-level verification.
Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
Collaborate across verification teams on vertical and horizontal reuse of components.
Define and implement functional coverage and drive coverage closure.
Triage and debug testbench, simulation, and emulation fails.
Write makefiles and scripts for verification infrastructure.
Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
Provide technical leadership through mentorship and teamwork.
Embody our Culture and Values
Qualifications
Required/Minimum Qualifications
11+ years of related technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience or internship experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
10+ years of experience in design verification with a proven track record of delivering high performance IP, SS or System on Chip testbenches.
10+ years of experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM)
10+ years of experience debugging Register Transfer Level (RTL) designs in simulation and emulation environments
Other Qualifications:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications
18+ years technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 15+ years technical engineering experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer
15+ years experience leading cross-functional / cross-time-zone engineering teams
Verification lead experience for multiple IP or SS related to Central Processing Unit (CPU), Vector Processing Unit (VPU), Graphics Processing Unit (GPU), Direct Memory Access (DMA) engine, Tensor unit (TU), or similar
Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
Experience in Scripting language such as Python or Perl
Experience in Formal property verification
Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $158,500 - $276,600 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $202,800 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until April 12, 2024.


Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

START NEW SEARCH