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Includes verification principles, testplan development, testbench creation, stimulus generation, Universal Verification Methodology (UVM) and coverage, debugging designs as well as creating simulation environments, with full verification cycle on complex SoC IPs and/or systems.
$282,200 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus. Senior Design Verification Engineer. We need someone with good verification skills and preferably some experience with Arm IP and architecture.
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This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification.
$170,000 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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This is a role for a versatile engineer that includes RTL design, verification, Emulation/FPGA partitioning and implementation, and lab based bringup of the SoC/GPU chips. + Extensive design verification experience (RTL, Emulation, or Prototyping.
$356,500 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Kelly Science, Engineering, Technology, and Telecom a managed solution provider and business unit of Kelly Services, is currently seeking a Sr Systems Verification Engineer for a long-term engagement at one of our Global Medical Device Robotics & Digital Solutions clients in Santa Clara, CA. A global leader in surgery with products and solutions found in almost every operating room around the world.
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Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows. Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology.
ExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Experience developing verification environments in one or more industry standard languages like SVTB, UVM/OVM. The DV team at Ampere Computing comprises of stellar folks who have dedicated themselves to the art and fun of design verification.
$194,000 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system.
$230,000Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Job Title: Senior Design Verification EngineerLocation: Mountain View CARole Type: Permanent FulltimeWhat You'll Be Doing:Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
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JOB TITLE: Accelerator Verification Engineer. Join a cutting-edge hardware startup in Silicon Valley as a Silicon Verification Engineer. Own the top level verification for an AI/analytics accelerator.
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They are looking for a principal-level Design Verification Engineer to join their team as they create best-in-class silicon for high-performance and sustainable GenAI. Hands-on experience with advanced verification methodologies such as UVM and assertion-based verification (ABV); a strong familiarity with both formal and simulated verification techniques is essential.
$350,000 a yearFull-timeExpandApply NowActive JobUpdated Yesterday - UpvoteDownvoteShare Job
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In this role, you will work closely with Architects and ASIC Engineers to define and implement test plan, own all tasks involved in verification sign off to deliver high quality IPs, which are used in NVIDIA products around the world.
$247,250 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Verification of a new hardware block for dot-product based attention. Collaborate with the hardware team to root-cause and fix bugs identified during verification. Have a deep knowledge of Verilog and UVM.
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Develop appropriate assertions to enforce analog/digital specs are respected and provide digital verification passing criteria. Assess required model accuracy level depending on verification goals.
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In depth knowledge of verification principles, testbenches, stimulus generation and UVM based test environments. Role: Design Verification Engineer. Plan the verification of complex design IP/SoC like CPU/Core/GFX block.
$100,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago
Title: insurance verification in Mountain View, CA
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