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Job Description: Role: Design Verification Engineers (SoC-5, PCIe-5) Location : Bay Area (Mountain View or San Jose, CA) Salary: 160-240k (DOE) Free health insurance PTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description : Architect block and full-chip verification environments using HVLs and constrained random.
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Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular System Verilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow.
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Tulane University School of Medicine invites applications for a research scientist position in the Department of Medicine as a member of the newly established school-wide Center for Health Outcomes, Implementation and Community-Engaged Science (CHOICES).
Full-timeExpandApply NowActive JobUpdated 25 days ago - UpvoteDownvoteShare Job
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Exposure to various ASIC design verification tools with good digital design concepts. We are seeking an experienced Senior Staff Verification Engineer. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification and constrained random generators, and reference model-based checkers.
$230,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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The Verification Engineer will ensure the fidelity of new highly configurable cores and other related IPs, for clients taking on exciting new use cases—like autonomous driving, 5G networking, wearables, or IoT.
$189,175 a yearFull-timeExpandApply NowActive JobUpdated Yesterday - UpvoteDownvoteShare Job
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Senior ASIC Verification Designer in San Jose, United States. 8+ years of experience in ASIC/FPGA verification including writing verification test plans, verification environment development behavioral model development and test case writing.
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Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications.
$203,000 a yearFull-timeExpandApply NowActive JobUpdated 20 days ago - UpvoteDownvoteShare Job
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Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. SOC Verification experience using ARM Cortex Microcontroller is required.
Full-timeExpandApply NowActive JobUpdated 17 days ago - UpvoteDownvoteShare Job
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BSc in Electrical Engineering or Computer Engineering 8+ years of experience in Mixed Signal Design Verification or MSc in Electrical Engineering or Computer Engineering with 6+ years of of experience in Mixed Signal Design Verification.
$178,000 a yearFull-timeExpandApply NowActive JobUpdated 21 days ago - UpvoteDownvoteShare Job
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Experience with advanced peripheral bus Verification IP's such as GPIO, UART, SPI, SW, JTAG, and I2C. Role: Design Verification Engineer. Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
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As the Advanced Design Verification Engineer , you will lead next-generation ASIC infrastructure initiatives, including the development of tools and infrastructure targeting efficiency and reuse spanning DV, Emulation, pre, and post-silicon.
$170,000 a yearFull-timeExpandApply NowActive JobUpdated 21 days ago - UpvoteDownvoteShare Job
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As a Design Verification Engineer, you'll be integral to ensuring our SoC ASICs meet the highest standards of performance and reliability. Familiarity with power intent verification (UPF), design prototyping on FPGAs, and emulation systems such as HAPS & Zebu is especially attractive.
$205,000 a yearFull-timeExpandApply NowActive JobUpdated Yesterday - UpvoteDownvoteShare Job
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You will be responsible for building and continuously improving verification infrastructure and methodologies to meet the demands of next-generation SoCs. This position offers the opportunity to collaborate closely with system architects, RTL designers, FPGA, and emulation engineers to ensure verification requirements and coverage are met for each project.
Full-timeExpandApply NowActive JobUpdated 15 days ago - UpvoteDownvoteShare Job
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Kelly Science, Engineering, Technology, and Telecom a managed solution provider and business unit of Kelly Services, is currently seeking a Sr Systems Verification Engineer for a long-term engagement at one of our Global Medical Device Robotics & Digital Solutions clients in Santa Clara, CA. A global leader in surgery with products and solutions found in almost every operating room around the world.
Full-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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Ambarella designs complex SoCs which include custom DSP and computer vision blocks, CPUs and co-processors.
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Title: insurance verification Company: Insight Choices in San Jose, CA
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