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A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.
$230,000 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. SOC Verification experience using ARM Cortex Microcontroller is required.
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In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification. + Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
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High technical competence that includes a track record of effective verification of complex digital designsSolid understanding of standard ASIC verification techniques, including:Test planningTestbench creationCode and functional coverageDirected and SystemVerilog-based constrained random stimulus generationSelf-checking - scoreboards, predictors, or reference modelsAssertions.
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This is a role for a versatile engineer that includes RTL design, verification, Emulation/FPGA partitioning and implementation, and lab based bringup of the SoC/GPU chips. + Extensive design verification experience (RTL, Emulation, or Prototyping.
$356,500 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Job DescriptionSenior E/E & Semiconductor Engineer - Mixed Signal Verification Engineer-DescriptionPosition- Mixed Signal DV Engineer Location-Sunnyvale CA - Onsite roleJob description:We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills and experienced with gate level parasitic annotated simulations.
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Understand medical device quality management systems (QMS) Must be able to function independently and work in a team Knowledge of SW Python (Python and MATLAB, and some Linux) Mechatronics/Capital system/Integrated HW + SW preferred Test method, design verification, documentation experience desired (Agile/PLM, test cases, protocol, IQOQ, etc.
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As Emulation Verification engineer, you will play a key role in preparing the wireless SoCs ready for emulation build by adding suitable monitors/checkers and sanitizing with testcases in emulation TB. Once the emulation build is ready, you will work on coming up with acceptance tests and executing the same on the emulation platform.
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You will be responsible for RTL SoC/Subsystem verification of ARM based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows.
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Position Title : Sr ASIC Design Verification Engineer. As a member of the development team, you would implement and execute SV/UVM based Verification environments. 10+ years of experience with SV/UVM based Verification environments including agents, scoreboards, coverage and randomization will be required.
$180,000 a yearFull-timeExpandApply NowActive JobUpdated Yesterday - UpvoteDownvoteShare Job
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5+ years of experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
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We are looking for ASIC verification engineers to join our rapidly growing engineering team focused on breakthrough cloud and data center infrastructure solutions involving both storage and computing.
$180,000 a yearFull-timeExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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A seasoned Design Verification Engineer with over 10 years of experience to join their team in San Jose. The ideal candidate will have extensive expertise in PCle protocol and hands-on experience in ASIC/FPGA design verification.
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5) Implementing test plans into executable test suites using a cutting edge System Verilog verification environment as well as leveraging high performance verification platforms such as test bench acceleration and In-circuit emulation as required.
$163,000 - $260,000Full-timeExpandApply NowActive JobUpdated 2 months ago - UpvoteDownvoteShare Job
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Implement and maintain RTL specifications and verification environments using System Verilog, ensuring system-level test scenarios and coverage plans for AI microchips. Principal Design Verification Engineer.
Full-timeExpandApply NowActive JobUpdated 1 month ago
Title: verification Company: Insight Choices in San Jose, CA
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