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As a Verification Engineer with expertise in subsystems and SoCs, you will be responsible for verifying the functional correctness of RTL for infrastructure SOCs. You'll collaborate closely with the project team to understand subsystem architecture, review design specifications, and develop a comprehensive verification strategy.
Full-timeExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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The Verification Engineer will ensure the fidelity of new highly configurable cores and other related IPs, for clients taking on exciting new use cases—like autonomous driving, 5G networking, wearables, or IoT. The Verification Engineers will be responsible for adopting state-of-the-art verification methodologies to in-house designs in order to ensure that everything on SiFive’s integrated circuits work as intended.
Full-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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5+ years of ASIC/FPGA verification experience using SystemVerilog / UVM. Designing and implementing SystemVerilog / UVM test benches for constrained-random verification. Deliver consulting services covering functional verification flow implementation.
ExpandApply NowActive JobUpdated 16 days ago - UpvoteDownvoteShare Job
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8+ years of practical design and verification experience using SystemVerilog UVM and ASIC verification. Analog Mixed Signal Design Verification Engineer. Synapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position.
Full-timeExpandApply NowActive JobUpdated 11 days ago - UpvoteDownvoteShare Job
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Design Verification Developing UVM and/or Formal-based verification architectures and methodologies. Fluent in writing protocols, compiling, Hardware verification, and firmware. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
ExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. SOC Verification experience using ARM Cortex Microcontroller is required.
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Simulation software for FPGA functional verification. Proficient in design verification tools and languages (SystemVerilog, SVA, Modelsim, Perl,Python, Unix shell scripts) Experience in the chip level verification environment setups, code/functional coverage collection.
ExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Job Title: BMS Software Verification Engineer. -Create high-level and low-level test frameworks that allow complex verification of real- -Participate in the creation of verification strategies, plans and procedures, including test.
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This position requires expertise in ASIC verification methodologies, including OVM (Open Verification Methodology) or UVM (Universal Verification Methodology), as well as proficiency in Verilog.
$145,000 - $160,000 a yearFull-timeExpandApply NowActive JobUpdated 8 days ago - UpvoteDownvoteShare Job
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What You’ll Do:In the Sr. BMS Verification Engineer role, you will verify that Archer’s high voltage battery management and charging systems satisfy their requirements – enabling the use of electric vertical-takeoff-and-landing aircraft for urban air mobility.
$134,400 - $168,000 a yearFull-timeExpandApply NowActive JobUpdated 11 days ago - UpvoteDownvoteShare Job
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Creates and maintains verification test benches and environments in System Verilog/UVM. Verification skills: Test planning, Scripting, Simulation, problem solving and debug. Responsible for verification of Graphics IP , and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met.
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This Principal level position is primarily an FPGA design and verification position with emphasis on video display and camera systems. Advanced skills with FPGA Design and Verification. Process Control - Requirements capture through formal verification (DO-254.
ExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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So, if you are a Principal ASIC Design Verification Engineer with UVM and PCIe and/or CXL experience, please apply today! Job Title: Principal ASIC Design Verification Engineer - UVM, PCIe, CXL.
$180,000 - $240,000 a yearFull-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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Note: - Current state-of-the-art testbench development such as UVM methodology - Experience in design verification with UVM and SystemVerilog is a MUST Responsibilities " Triage regression failures and make testbench updates " Debug functional errors in RTL model using simulation and debug tools.
$80 - $100 an hourExpandApply NowActive JobUpdated 2 months ago - UpvoteDownvoteShare Job
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Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data center applications.
$95,400 - $133,000 a yearFull-timeExpandApply NowActive JobUpdated 10 days ago
Title: verification Company: Communitybank Of in Milpitas, CA
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