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Design Verification Engineer with UVM, OVM, SystemVerilog & Python
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- Role: Design Verification Engineer
- Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
- Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
- Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
- Strong knowledge in SV Assertions, UVM/OVM and functional code coverage.
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