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Applications Engineering Intern
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Intern
- With this training, you will be responsible for implementing a partition to meet specific power, performance, and area (PPA) targets.
- Gaining exposure to the most current technology nodes, allowing you to analyze the design and apply strategies to meet PPA goals.
- You will be involved in tasks such as logic synthesis, floor planning, power planning, placement, congestion analysis, clock tree synthesis, routing, timing analysis and DRC closure.
- Understanding of Physical Implementation Flow and Knowledge of EDA Tools (Beginner)
- Our Silicon Design & Verification business is all about building high-performance silicon chips—faster.
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