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Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc. Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.
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They are searching for a Staff Mixed-Signal Verification Engineer to join their IoT Digital Design team to take a pivotal role in the delivery of flawless wireless SoCs packed with cutting-edge tech supporting a range of wireless standards, custom RISC-V cores, and AI/ML modules.
$150,000 - $250,000 a year (bonuses)Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Senior Digital Design Engineer - SOCAustin, TXMeet the TeamThe IoT Digital Design team is a state-of-the-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of the IoT Digital team.
$114,428 - $212,510 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs.
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Low Power intent verification using CPF, UPF. Development of verification test bench components such as drivers, monitors, and response checkers as well as use of most advanced UVM VIPs.
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Design using Verilog, logic simulation, functional verification, & synthesis of DSP & data conversion ICs in a mixed signal environment. The position also requires coursework in or equivalent knowledge of Digital Integrated Circuit Design, Advanced VLSI Design, Hardware verification; the ability to perform RTL coding using Verilog, System Verilog; proficiency with languages like C/C.
Full-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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This included physical design of multilevel boards including DFM (Design for Manufacturing), power regulation, board bring-up qualification and debug, thermal, signal integrity, EMI (Electro-Magnetic Interference.
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Candidate will also perform sustainment of design of a standalone functional test setup, planning and execution of Environmental Design Verification Testing (DVT), EMI DVT, EIB, and Power Transfer, support to integration with the other test equipment or hardware including Telemetry Interface, support to testing at remote location or lab, and support integration and functionality in the Hardware in the Loop (HWIL) lab for an upcoming flight test.
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Job DescriptionRenesas is seeking a SoC/IP Verification Engineer for our Infrastructure Power team in Austin, TX, where we develop the most advanced digital power IC’s in the industry.
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A strong background in Low Power architectures or verification is a plus. We are looking for a Senior Low Power DV Engineer! MSEE/MSCE (or equivalent experience) with background in ASIC design verification.
$124,000 - $247,250 a yearFull-timeExpandApply NowActive JobUpdated 3 months ago - UpvoteDownvoteShare Job
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This industry leading performance per watt CPU helps power the latest generation of Intel laptops and desktops, 5G base stations, micro-servers and other Artificial Intelligence and Machine Learning devices.
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DPI Transactors, Accelerated UVM Testbenches, SV assertions, Coverage, Power Estimation, SpeedBridges -SoC and IP bringup on emulation, root cause UVM and SoC CPU test and emulator environment issues -Role requires close collaboration with Design, DV, Power, Silicon Validation, Performance and Software teams.
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Description : DFT Job Responsibilities: · Use industry standard tools to implement scan in complex IP, and generate high coverage ATPG patterns utilizing scan compression and verification. · Knowledge of low-power design methodologies.
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Develop and maintain flows, scripts and systems around the RTL and Verification development work cycle like RTL simulators, Low-Power checkers, Coverage etc. In this visible, multi-functional role, you will be part of a high-functioning and diverse Front End CAD team that defines, develops, tests and supports RTL and Verification CAD tool flows such as RTL simulation, emulation and CI/CD for behavioral models.
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Business group: In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. Intel or industry experience in micro-architecture, design or verification of CPU cores.
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verification engineer power jobs in Austin, TX
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