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Title: Design Verification Engineer. Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage. · A minimum of three years of experience with SoC Design Verification.
$80 an hourFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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A seasoned Design Verification Engineer with over 10 years of experience to join their team in San Jose. The ideal candidate will have extensive expertise in PCle protocol and hands-on experience in ASIC/FPGA design verification.
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As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
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We are looking for ASIC verification engineers to join our rapidly growing engineering team focused on breakthrough cloud and data center infrastructure solutions involving both storage and computing.
$180,000 a yearFull-timeExpandApply NowActive JobUpdated 4 days ago - UpvoteDownvoteShare Job
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Exposure to various ASIC design verification tools with good digital design concepts. We are seeking an experienced Senior Staff Verification Engineer. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification and constrained random generators, and reference model-based checkers.
$230,000 a yearFull-timeExpandApply NowActive JobUpdated 1 month ago - UpvoteDownvoteShare Job
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Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus. Senior Design Verification Engineer. We need someone with good verification skills and preferably some experience with Arm IP and architecture.
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Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows. Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology.
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Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interconnect Design team in San Jose, California. As a Principal Verification Engineer, the candidate will be reporting to the Director of Design Engineering and is a Full-Time position.
$251,700 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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JOB TITLE: DFT Verification Engineer. Work with verification engineers, stepping in to do run tests when needed. Some Design Verification experience. JOB TITLE: DFT Verification Engineer.
Full-timeExpandApply NowActive JobUpdated 1 month ago - UpvoteDownvoteShare Job
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Lead Verification Engineer with 12+ years of experience. Hands on experience on Arm based SoCs, leading a team of Verification Engineers locally as well as at different geographical site.
$165,000 a yearFull-timeExpandApply NowActive JobUpdated 3 months ago - UpvoteDownvoteShare Job
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Support performance verification, power-aware simulation, RTL/FW co-simulation, and GTL simulation. - Industry experience as Design Verification Engineer. - Improve and refine verification process.
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Verification of Tenstorrent's digital IP and SOC logic at chiplet integration level, using a predominantly UVM based verification methodologies. Create verification components including but not limited to creating testbenches, checkers and monitors, and test generators.
$500,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.
$100 an hourExpandApply NowActive JobUpdated 15 days ago - UpvoteDownvoteShare Job
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Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. Architect block and full-chip verification environments using HVLs and constrained random. Evaluate latest verification methodologies and develop scripts etc.
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Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus. Expert knowledge of state-of-the-art verification flow and methodology, such as constrained random, functional/code coverage, assertions, GLS.
$293,800 a yearExpandApply NowActive JobUpdated Today
Title: verification Company: Working Solutions in Sunnyvale, CA
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