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Sr. Synthesis & Front - End STA Engineer (Silicon Engineering)
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$220,000 a year
Full-time
- We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
- Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
- Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
- Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock domain crossing flows
- Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs - generally bridging the RTL and place and route
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