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Senior DFT Engineer
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$143,000 - $215,000 a year
Full-time
- The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs.
- The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations.
- The ideal candidate will have experience in both pre, and post-silicon in the DFT domain
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
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