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PE Digital Engineering
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- Rambus, a premier chip and silicon IP provider, is seeking an exceptional Principal Digital Design Engineer to join our Buffer Chip Design?
- As a Principal Digital Design Engineer, the candidate will be reporting to the Technical Director, Engineering in a Full-Time capacity.
- Implementation: RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top level integration, synthesis, timing analysis, timing closure, DFT-related tasks
- 7+ years of relevant digital/ASIC/IC design experience
- Significant Experience with RTL coding in Verilog and/or VHDL
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