Cisco

With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.. Drive the review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.. Drive SoC Physical Design Implementation in Advanced Process Nodes with world class team of Physical Design, Circuit design, DFT and integration engineers.. Maintain close interactions with RTL, NPI, Packaging, DFT, Architecture teams.. Drive ASIC design methodology and flow from concept to release.

director

Who We Are   The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.   What You Will Do  <ul><li>Closely work with Team Leads to Build PD Execution Schedule and Track Milestones through the Project. </li><li>As a Soc Physical Design Lead, you will work closely with Architecture/Package/PD Teams to develop, craft, and optimize floor-plans during early chip development to meet Power/Performance/Area Goals for the SoC. </li><li>Drive the review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. </li><li>Build tools and improve existing infrastructure to optimize chip area and speed of execution. </li><li>Interact with Design team to review constraints. </li></ul> Your Responsibilities Will Include <ul><li>Collaborate with Cross Functional Teams across geographies. </li><li>Drive SoC Physical Design Implementation in Advanced Process Nodes with world class team of Physical Design, Circuit design, DFT and integration engineers. </li><li>Build a team of hard-working and passionate leaders as we scale. </li><li>Develop Soc Execution Schedule and Milestone Tracking. </li><li>Communicate Status and Risks to Senior Management. </li><li>Expert understanding of both FE and BE ASIC flows. </li><li>Maintain close interactions with RTL, NPI, Packaging, DFT, Architecture teams. </li><li>Own power, performance and area optimization of design. </li><li>Oversee the development of new automation utilities for improved quality, time to delivery and high-quality Designs. </li><li>Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work. </li><li>EMIR analysis and Timing signoff closure. </li></ul> Minimum Qualifications   <ul><li>Demonstrable management experience in leading a team that does SoC and Physical Design. </li><li>Drive ASIC design methodology and flow from concept to release. </li><li>Previous demonstrated experience at leading and managing large ASIC developments in advanced process nodes. </li><li>Demonstrable hands-on experience in ASIC design. </li></ul>Preferred Qualifications   <ul><li>Knowledge of industry standard PnR and signoff tools and their capabilities. </li><li>Understands the big picture and attention to detail during execution. </li><li>Prior Experience in developing Physical Design execution Schedule. </li><li>Knowledge and hands on experience in block level synthesis, place and route, timing closure. </li><li>Understanding advanced power analysis and power integrity analysis. </li><li>Knowledge of scripting languages Tcl, Python. </li><li>Manage Static Timing Analysis, timing closure and design constraints. </li><li>Self-motivated, able to work in a highly cross functional team. </li><li>MS or Bachelor’s in Electrical Engineering or Computer Science. </li></ul>Why Cisco <li> </li>  #WeAreCisco, we are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters - with people like you!   Nearly every internet connection around the world touches Cisco. We’re the Internet’s optimists. Our technology makes sure the data travels at light speed across connections does so securely, yet it’s not what we make but what we make happen which marks us out. We’re helping those who work in the health service to connect with patients and each other; schools, colleges, and universities to teach in even the most complicated times. We’re helping businesses of all shapes and sizes to connect with their employees and customers in new ways, providing people with access to the digital skills they need and connecting the most remote parts of the world - whether through 5G, or otherwise.   We take on challenges that come our way. We have each other’s backs and recognize our accomplishments as we grow together. We celebrate and support one another - from big and small things in life to big career moments. And giving back is central to our purpose (we get 10 days off each year to do just that).   We know that powering an inclusive future starts with us. Because without diversity and a dedication to equality, there is no moving forward. Our 30 Inclusive Communities, that bring people together around commonalities or passions, are leading the way. Together we’re committed to learning, listening, caring for our communities, whilst supporting the most vulnerable with a collective effort to make this world a better place either with technology, or through our actions. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. A passion for technology and world changing? Be you, with us!   #WeAreCisco

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