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This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification.
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As the FPGA Engineer for Axiado, you will have the opportunity to work in design verification, debug and system integration. You will work closely with the Architecture, Verification, ASIC Design and Software teams, and report into the Engineering organization.
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Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route. Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification.
$230,000Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime). - Oversee the floorplan layout and verification of the design to ensure a successful tape-out.
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Core DFT skills for this position should include some of the following: Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
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Perform PCB design verification and testing. Once designer completes design, you will need to review the schematic and/or layout files to ensure that the documentation meets the requirements of the customer and follows chamber requirements/limitations as well.
$90,451 a yearExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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As a member of the team you will work with top industry talent and contribute in system architecture, network processor (NPU) architecture, Ethernet processing, digital signal processing, modeling, high-speed logic design & verification, custom processor development, dense and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology.
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Must have at least 4 years of experience in managing ASIC design, integration, or verification teams. Experience in using UVM for functional verification of ASIC designs. Extensive experience with FPGA emulation, design tools, and verification.
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As the Lead Layout Designer, you will work closely with semiconductor design engineers in the layout and verification of RF, analog and mixed signal integrated circuits for wireless consumer electronic products.
$210,600 a yearFull-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Proven experience in state-of-the-art verification methodologies including SV/UVM, Coverage driven verification, and formal verification. Participate in the definition and deployment of industry-standard verification and validation methodologies.
$307,400 a yearFull-timeExpandApply NowActive JobUpdated 17 days ago - UpvoteDownvoteShare Job
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We are seeking a highly skilled Automation and Verification Engineer to join our dynamic team, driving robustness of hardware, software, firmware, and algorithms into systems that shape the future of medical science.
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As a member of the mixed signal team, the candidate's work encompassing the development of the state of the art mixed signal IP for SOC including SerDes, PLL, DDR PHY, MIPI PHY, candidate will have exposure to a broad range of IP design phases, including analog circuit level transistor design, IP top level mixed-mode modeling, digital system RTL design, verification, synthesis, STA analysis, simulation and verification in mixed-signal IC environment.
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We offer: Competitive pay rates Free, quality, private housing Medical, Dental, Vision 401(k) and Flex Spending Life Insurance Accident and Short-term Disability Coverage Free Continuing Education Refer a friend and earn extra cash.
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Skilled using design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA) Be responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies.
$258,750 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Processor verification, UVM, SOC verification on FPGA, complete verification cycle, Make/Perl/Python, Test bench. Job Title: Design Verification Engineer. NOTE: Design verification role and should have experience in System Verilog HVL, C.
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insurance verification jobs Title: representative patient customer service in Santa Clara, CA
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