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As a Senior Signal Integrity Engineer, you would be responsible to design the chain of interconnects for Nokia's fiber-optic transceiver products. Drive cross-functional discussions to analyze the full signal path from DSP ASIC, through the RF interface to the module, followed by the driver/TIA and Silicon-Photonic Integrated Circuit.
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Applied knowledge in signal integrity, printed circuit boards, material science and basic chemistry is beneficial. Experience with design and analysis tools including Solidworks, Creo, Ansys, Icepack is plus.
$138,900 - $256,500 a yearExpandApply NowActive JobUpdated 8 days ago - UpvoteDownvoteShare Job
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Hands-on experience in all aspects of schematic capture, PCB design, as well as understanding signal integrity, mechanical and thermal design areas. Hands on responsibility for the schematic capture, PCB design and other aspects of the hardware system around a complex custom AI ASIC.
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System/Board Design, Circuit Board Layout, Signal Integrity, Power Design. ASIC Design, Verification. System/Board Design, Circuit Board Layout, Signal Integrity, Power Design.
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Must have experience with high-speed SERDES (>=25G) system design, signal integrity issues, and power distribution techniques. Ability to interface with other cross-functional teams, including CAD, FPGA, Power, Mechanical, Signal integrity and Manufacturing teams.
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In addition, Phison already has an established ASIC design service, offering IP licensing, firmware development, Phison’s Vertical Integration of Controller ASIC. Phison understands that success in today’s fast-paced market requires more than just providing NAND storage solutions; it requires the ability to influence and shape the industry through signal integrity and power management ICs, Compute Express Link.
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We are not looking for expertise in ASIC - components (FPGA components from board design point of view, not RTL or coding. Hands on board design knowledge, familiar with design tools including Cadence Concept, and Allegro.
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Work on Signal Integrity solutions to complex system design problems. Opportunity to work in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.
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Good understanding of cross-functional packaging areas: Si floor plan, package and board level layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, reliability, and cost.
$175,000 - $200,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Work with ASIC, system and signal integrity team to evaluate design tradeoffs, optimize design solutions and review SI/PI designs. You will work with Design team, Signal Integrity team, Routing SW/HW team, SDK team, Production and Assembly team.
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As a Signal Integrity/Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package, and system level.
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BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 2+ years’ experience in ASIC Design and Timing. Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills as well as physical design/circuit skills for timing closure.
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ASIC design experience with Simulation/Verification and RTL Synthesis is required. Knowledge of competitive EDA tool products and product knowledge in any of the areas of P&R, Physical Verification, Signal Integrity is highly desired.
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Knowledge of timing corners/modes, process variations and signal integrity related issues and modeling. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team.
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P&R construction flows and analysis flows for PPA (performance, power, area) and reliability (signal/power integrity, etc.) Join a cutting-edge and well-funded hardware startup as a Physical Design CAD Engineer.
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asic design signal integrity jobs in Santa Clara, CA
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