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Drive improvements into static verification methodology PREFERRED EXPERIENCE: Exposure to power (UPF) / Clock domain crossing Having practices in formal verification Experience with emulation based power analysis Having RTL level power estimation experience is a plus x86 Architecture knowledge preferred Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Experienced with Verilog, System Verilog, Experience with C/C.
Full-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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About the role As a senior member of Recogni's software team, you will be responsible for implementing the software that runs inside a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company's flagship perception module product for autonomous driving applications.
Full-timeExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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As a member of Recogni’s ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
ExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the first tape out success on designs - generally bridging the RTL, and place & route worlds.
ExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA.
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Experience using all types of electronic test equipment (Oscilloscopes / power supplies) Knowledge in Intel/AMD/Nvidia chipset, functional safety, and in-vehicle server product is a plus. Involve in our next generation HPC’s development and verification.
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Other circuit design projects may include working with analog and logic sections of the following: Amplifiers, Variable Gain Amplifiers, Operational Transconductance Amplifiers, Class AB Power Amplifiers, sigma delta D/A converters for Audio, sigma delta A/D converters for Audio, low noise switched capacitor or OTfilters, voltage & current references, PLL, VCO, charge pump & DC-DC converters.
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This young and ambitious AI company are currently seeking a Senior ASIC Verification Engineer to be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC.
ExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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The Physical Design Intern will support the following areas within the physical design team; floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.
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5+ years of meaningful experience with all stages in the ASIC design flow including functional and formal verification, emulation, DFT, synthesis & timing analysis, power estimation and ECO.
$124,000 - $247,250 a yearExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
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As a senior member of Recogni’s ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
ExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Perform ASIC design flow enablement, execution, PPA (Power, Performance, Area) analysis, synthesis, APR, and layout verification. Experience in digital circuit design, front end model creation and functional verification.
$91,500 - $137,436 a yearFull-timeExpandApply NowActive JobUpdated 16 days ago - UpvoteDownvoteShare Job
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Responsibilities include: - Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. - Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
$160,700 - $282,500 a yearExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route. Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification.
$170,000 - $230,000Full-timeExpandApply NowActive JobUpdated 6 days ago
verification engineer power jobs in San Jose, CA
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