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Verification of the ASIC design, architecture, golden models, and micro-architecture using sophisticated verification methodologies such as UVM. Experience in writing UVM testbench from scratch and applying constraint random methodology in UVM test environment.
Full-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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SystemVerilog and UVM. IP/SOC/ASIC DV engineer responsible for planning and coordinating the design verification, and evaluation in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality.
ExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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As a Design Verification Engineer with this company you will work with test bench development using System Verilog and UVM as well as develop comprehensive test plans and cases with functional coverage, assertions, and coverage properties.
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Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation. In this position, you will get the opportunity to build complex GPU and Tegra chips and interface, directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
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System Verilog, UVM, Verilog or VHDL, C/C. Creates and maintains verification test benches and environments in System Verilog/UVM. System Verilog, UVM, Verilog or VHDL, C/C. Creates and maintains verification test benches and environments in System Verilog/UVM.
$170,500 - $255,500 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular System Verilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow.
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Proficiency in UVM verification environment. Our DDR PHY IP team is Hiring a Staff level Digital ASIC Verification Engineer. ASIC Design Verification Engineer, Senior Staff. Experience in ASIC Verification at the SOC level and block level.
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Experience with constrained-random, coverage-driven automated verification using module-to-system level reuse methodology (e.g. UVM, OVM, VMM, eRM), using hardware verification languages such as SystemVerilog.
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Background with System Verilog and UVM based methodology for ASIC verification. Background with System Verilog and UVM based methodology for ASIC verification. NVIDIA is seeking hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs.
$128,000 - $258,750 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Develop top/block level Mixed Signal and Digital testbench and generate directed and randomized tests in an SV/UVM framework. Experience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog) for verification.
ExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Identify design features for verification and functional coverage within verification tools such as System Verilog, UVM, and Verdi, among others. Develop and maintain System Verilog/UVM test benches.
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Design Verification – Implement test benches in UVM and System Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
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Experience with UVM (or similar). As a senior member of Recogni’s ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
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Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM. Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
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Knowledge of UVM is a plus. languages, digital image processing and chip-level tape out procedure from initial PRD, design, verification, timing closure, FPGA emulation and ECO. Minimum of 10 years plus of ASIC design experience with knowledge of ASIC design flow, including hands-on experience in ASIC chip design and integration.
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uvm job in San Jose, CA
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