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Sr. Mixed - Signal Verification Engineer
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- Sr. Mixed-Signal Verification Engineer
- In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests.
- Review specifications, extract features, define and execute verification plan in coordination with architects and analog designers -Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.
- Develop top/block level Mixed Signal and Digital testbench and generate directed and randomized tests in an SV/UVM framework.
- Industry verification experience with RF/Mixed-Signal blocks and SOCs.
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