Lead Board Hardware Debug Engineer – Datacenter & AI Platforms

Overview In this Senior Board Hardware Debug Engineer role, you own complex board-level debug for high-performance Datacenter GPU platforms and drive hardware validation from prototype bring-up to production. You analyze and optimize board signaling and system design to support next-generation GPU-based solutions, working across CPUs, memory, networking, and power delivery. You lead cross-team system-level integration and debug on multi-board, multi-GPU platforms, ensuring performance, reliability, and quality in demanding AI environments. This is an opportunity to shape hardware validation practices at scale and contribute to bold, innovative datacenter solutions at AMD. ResponsibilitiesLead board- and system-level debug of Datacenter GPU platforms (bring-up, stability, performance, interoperability)Develop and execute functional test plans for new boards and system configurationsPerform and guide Board Signal Integrity validation: eye diagrams, jitter analysis, margins, channel characterizationLead technical validation efforts across teams, driving validation priorities and test coverage for critical featuresChampion root-cause analysis and cross-functional debug across silicon design, firmware, BIOS, board design, and manufacturingCollaborate closely with hardware design, layout, SI/PI, firmware, BIOS, and system engineering teams to resolve issuesProvide design-for-test and design-for-debug feedback for future board and system designsDocument debug findings, create reproducible test cases, and drive corrective actions into design and processSupport factory, customer, and field escalations requiring deep hardware debug expertise Key requirementsDatacenter board design or board validation experience for server, accelerator, or networking productsStrong background in system-level hardware validation (bring-up, qualification, reliability, margin verification)Hands-on debug methodologies: fault isolation, boundary scan, probing, rework, A/B comparisonSolid understanding of signal integrity concepts and tools (high-speed SerDes, DDR, PCIe channel analysis)Working knowledge of computer and I/O protocols (PCIe, CXL, DDRx, NVLink, Ethernet, I2C/SMBus, SPI)Strong grasp of system architecture: CPU/GPU/memory hierarchy, power sequencing, reset schemes, clocking architecturesComfortable with lab equipment: high-speed oscilloscopes, logic analyzers, protocol analyzers, BERTs, VNAs/TDRsWilling and able to travel domestically and internationally for builds and debug eventsSelf-directed and able to manage multiple debug threads in parallelBachelor’s or Master’s in Electrical Engineering or related field, or equivalent practical experienceHands-on and lab-focusedProblem-solving and systematic debuggingCreative and resourceful, data-driven decision makinghigh-speed SerDes and PCIe analysissignal integrity and eye diagram analysisboard-level debug and test planning