Silicon Design Verification Engineer

Overview In this role you will join AMD's SOC Verification Team as a Silicon Design Verification Engineer to work on state-of-the-art verification of complex IP using SystemVerilog, UVM, and formal methods. You will own block- and subsystem-level testbenches, develop constrained-random and directed verification environments, and apply formal verification to ensure design correctness. You will collaborate with RTL engineers to optimize clock gating and verify multiple design aspects while tracking verification quality metrics. This is a hands-on, team-based role in a collaborative, innovation-driven environment that shapes next-generation silicon. ResponsibilitiesCreate test plans for complex IP designs with senior engineersDesign testbenches in SystemVerilog and UVM for efficient verificationDevelop constrained-random and directed verification environments; use SystemVerilog Assertions and formal toolsDebug tests with design engineers to close coverage and ensure functional correctnessCoordinate with RTL engineers to implement design improvements and verify clock gatingTrack verification quality metrics such as pass rates, code coverage, and functional coverage Key requirementsProject-level experience with design concepts and RTL implementationStrong understanding of computer organization/architecture and digital logic fundamentalsKnowledge of SystemVerilog and C++ (object-oriented concepts)Hands-on Python scripting for automationExperience with protocols like PCIe and AMBA AXI is a plusPrior UVM experience is a plusBachelor's or Master's in Computer Engineering or Electrical EngineeringTeam player with excellent communicationStrong analytical and problem-solving abilitiesWillingness to learn and take on challengesSystemVerilogUVMSystemVerilog Assertions (SVA)