Lead SMU Validation Engineer - Data Center GPU

Overview In this Lead SMU Validation Engineer role, you will own the validation of SMU hardware and power-management across pre-silicon to system-level enablement for AMD Data Center GPUs. You will partner with cross-functional teams to shape validation strategy for next-generation AI and HPC products. You’ll drive issue triage, root-cause analysis, and closure while mentoring engineers and improving validation methodologies. This position offers impact through enabling robust power-management and system-management features at scale in a dynamic, collaboration-focused environment. ResponsibilitiesPlan and execute SMU hardware validation across emulation, bring-up, post-silicon enablement, regression, and sustaining phasesDevelop validation plans for SMU sub-blocks and power-management features (bootcode, clocking, fuse, SMN, SMUIO, thermal, RSMU, security, and other system-management functions)Lead debug triage, root-cause analysis, and issue closure across hardware, firmware, platform, diagnostics, and system-level interactionsCollaborate with architecture, design, firmware, diagnostics, platform, automation, customer engineering, and program teams to align scope and risksBuild and improve automation, validation content, debug-analysis scripts, and regression checks to enhance coverage and repeatabilityReview RTL, specifications, firmware interfaces, register maps, and validation collateral to identify coverage gapsSupport lab-based and system-level debug using platform tools, firmware logs, register-level analysis, and standard equipmentAssist customer and sustaining issues with SMU expertise, debugging guidance, and issue-resolution supportMentor engineers and help improve validation methodology, debugging practices, and product quality Key requirementsStrong experience in semiconductor validation, silicon bring-up, SoC validation, firmware validation, or hardware/software integrationHands-on power-management validation, SMU/PMFW functionality, SoC control fabrics, clocking, reset, fuse, thermal, voltage-regulator, or platform-management featuresExperience developing validation plans, test content, automation, and debugging methodologies for complex SoC or GPU productsStrong debugging skills across hardware, firmware, software, diagnostics, and platform interactionsExperience with emulation, simulation, or FPGA/prototyping environmentsProficiency in Python and C/C++ for automation, test infrastructure, or debug-analysis toolsFamiliarity with Linux, lab bring-up, register-level debug, firmware logs, and platform debug toolsAbility to work independently, manage priorities, influence cross-functional teams, and drive issues to closureleadership and mentoringclear communication with technical and program stakeholdersproblem-solving and triagepower-management validationSMU/PMFW functionalitySoC control fabrics, clocking, reset, fuse, thermal, voltage-regulator