Staff Design Verification

Key ResponsibilitiesDevelop and execute verification plans based on design specificationsCreate testbenches using SystemVerilog, UVM, or similar methodologiesWrite test cases to validate functionality, performance, and corner casesPerform functional and code coverage analysisDebug design issues and collaborate with design engineers to resolve bugsUse simulation tools (e.g., VCS, ModelSim, Xcelium) to run testsDevelop reusable verification components and environmentsConduct regression testing and ensure design stabilityDocument verification results and provide detailed reportsRequired Skills & QualificationsBachelor's/Master's degree in Electronics, Electrical Engineering, or related fieldStrong knowledge of digital design fundamentalsExperience with HDL languages (Verilog/SystemVerilog)Familiarity with UVM (Universal Verification Methodology)Understanding of simulation and debugging toolsKnowledge of scripting languages (Python, Perl, or Shell)Good problem-solving and analytical skillsPreferred SkillsExperience with ASIC/SoC verificationKnowledge of formal verification techniquesFamiliarity with protocols (AXI, PCIe, USB, Ethernet, etc.)Exposure to coverage-driven verificationExperience with emulation or FPGA prototyping