Lead Design Verification Engineer (Fremont)

Strongly Preferred5+ years of Design Verification experienceDeep expertise with SystemVerilog and UVMExperience verifying AI accelerators, GPUs, TPUs, NPUs, DSPs, or high-performance SoCsStrong debugging skills across RTL, simulation, and system-level failuresExperience with constrained random verification, assertions, coverage closure, and regression infrastructureExperience owning DV for complex subsystems or full-chip environmentsBonus PointsExperience with coherency protocols, memory systems, NoCs, or high-speed interfacesExposure to formal verification methodologiesPython/C++ tooling experienceExperience improving verification productivity through automation or MLStartup or zero-to-one engineering experienceTapeout experience at advanced nodesCompensationWe offer highly competitive cash compensation and meaningful founding-level equity packages.