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Coding, and expertise in chip/full system level ASIC verification. Minimum 2 years of experience with chip/full system level ASIC verification skills. Minimum 2 years of experience with chip/full system level ASIC verification skills and debugging.
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PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
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Ability to develop specifications, cost, schedule, and resource requirements for FPGA or ASIC verification plans. Solid FPGA/ASIC Verification development methodology. Verify FPGA designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols), design and implement test benches for both unit level and system level environments and create reusable verification environments that can be used across multiple projects.
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We are seeking a highly experienced ASIC Design Verification Engineer to join our dynamic team. The ideal candidate should have a strong background in ASIC design verification, test planning, UVM, and scripting, with a passion for driving innovation and change in the industry.
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A minimum 5 years of experience in Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL. + Port ASIC and IP RTL code to prototyping and emulation platforms ( Zebu/HAPSs, Palladium/Protium.
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Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure. SoC Design, ASIC design, SoC architecture.
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Senior Staff ASIC Design Verification EngineerAbout this role: Groq is a machine learning systems company building easy-to-use solutions for accelerating artificial intelligence workloads.
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You will be responsible for interfacing with internal and external Honeywell ASIC-capability development teams and translating our mixed signal designs and digital library cells using Cadence and Mentor tools for physical design and verification.
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5+ years FPGA / ASIC design/verification skills experience. Verification background using System Verilog & UVM. That means changing the way we fly, fueling jets in an eco-friendly way, keeping buildings smart and safe and even making it possible to breathe on Mars.
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Ouster Inc. is seeking a digital hardware FPGA/ASIC design and verification engineering lead. You should be a hands-on technically savvy individual with a proven track record in FPGA/ASIC design processes with exposure into embedded software development.
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NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. Senior ASIC Verification Engineer.
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The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification.
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Job Title RTL ASIC Design EngineerJob Location San Jose, CA [Onsite Hybrid Work]Duration 12 Months [Contract job with potential extensions] RTL ASIC Design Engineer. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modelling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
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Preferred Qualifications:Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog) ASIC / FPGA lab validation with advanced lab equipment Design for Test (DFT) and manufacturability issues Experience with Unix, scripting, C/C.
$77,000 - $163,000Full-timeExpandApply NowActive JobUpdated 4 days ago - UpvoteDownvoteShare Job
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Required Education, Experience, & Skills Proficient in Verilog language for ASIC/FPGA design Knowledge of ASIC and FPGA design flows is highly desirable Knowledge simulation and verification methodologies (VCS simulator, UVM) Proficient in ASIC/FPGA timing closure/area optimization techniques Hands on Experience with bring-up of ASIC/FPGA designs Excellent organization and communication skills for interacting between different design groups Proficiency in C/C.
$143,000 - $243,100 a yearFull-timeExpandApply NowActive JobUpdated 10 days ago
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