Ouster

We've transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor.. Ouster Inc. is seeking a digital hardware FPGA/ASIC design and verification engineering lead.. You should be a hands-on technically savvy individual with a proven track record in FPGA/ASIC design processes with exposure into embedded software development.. FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis. Our newly renovated office, located in the Mission District of San Francisco, is a dog-friendly workplace with a kitchen stocked with snacks, fresh fruit and drinks, and a complimentary dinner catered nightly.

engineering lead

At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. We've transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor. The result is a full range of high-resolution LIDAR sensors that deliver superior imaging at a dramatically lower price. Our advanced sensor hardware and vision algorithms are used in autonomous cars, drones and many other applications. If you're motivated by solving big problems, we're hiring key roles across the company and need your help! Ouster Inc. is seeking a digital hardware FPGA/ASIC design and verification engineering lead. In this role, you are part of the Firmware team and will lead the effort to meet FPGA functional safety certification per the ISO26262 / ASIL-B specification. You should be a hands-on technically savvy individual with a proven track record in FPGA/ASIC design processes with exposure into embedded software development. Ideally, you should have strong experience in all aspects of FPGA subsystems including RTL design, verification and hardware bring up and debug. You should also have an excellent grasp of hardware/software codesign and interface concepts. You should be stickler for details and passionate about reliability and robustness of designs. Responsibilities: * Lead and perform safety analysis of FPGA subsystems* Drive and create functional safety documentation including V model requirements and FMEDA analysis* Define, develop, and integrate features across our FPGA stack with a focus on functional safety and reliability.* Enforce and refine FPGA development process to support functional safety needs.* FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis* Perform hands-on work using laboratory tools for board bring up and troubleshooting* Build automation scripts for repetitive tasks to facilitate efficiency and reliability Qualifications: * Bachelors in Computer Engineering, Electrical Engineering, or related field* At least 5 years FPGA development experience including HDL code development, simulation, test bench development, synthesis, and timing closure* Experience and understanding of safety concepts and ISO 26262, ASIL-B, or similar standards* Highly proficient with RTL development using Verilog and SystemVerilog* Proficient in some scripting languages such as Python, TCL, Perl, bash* Embedded system development experience in CPU and FPGA based devices such as Xilinx Zynq or Intel Arria devices.* Experience with Xilinx and/or Intel FPGA toolchain.* Experience with DSP algorithm implementations in FPGAs* Experience with processor architectures and various communications protocols such as DDR4, AXI, I2C, UART, SPI, ethernet, etc. Desirable Qualifications: * Familiar with HLS (High Level Synthesis)* Experience using best practices with version control technologies such as git* Proficient in C or C++ programming language* Familiar with leading verification methodologies like UVM $190,000 - $250,000 a year The starting base pay for this role is $190,000-250,000/yr. The base pay will be dependent on your skills, work experience, location, and qualifications. This role may also be eligible for equity & benefits. We acknowledge the confidence gap at Ouster. You do not need to meet all of these requirements to be the ideal candidate for this role. At Ouster we offer a range of competitive benefits, as we believe in taking care of our employees in all aspects of their lives. Our newly renovated office, located in the Mission District of San Francisco, is a dog-friendly workplace with a kitchen stocked with snacks, fresh fruit and drinks, and a complimentary dinner catered nightly. Additional perks include 15 vacation days/10 paid holidays annually; paid parental leave; pre-tax commuter or health care/dependent care accounts; 401K match up to 4%; medical, vision and dental plans with premiums covered at 100% for the employee and 75% for dependents (Cigna or Kaiser); life insurance; and short term disability and long term disability. Ouster offers the best benefit options available because we consider the well-being of our employees a top priority. Ouster is an Equal Employment Opportunity employer that pursues and hires a diverse workforce. Ouster does not make employment decisions on the basis of race, color, religion, ethnic or national origin, nationality, sex, gender, gender-identity, sexual orientation, disability, age, military status, or any other basis protected by local, state, or federal laws. Ouster also strives for a healthy and safe workplace, and prohibits harassment of any kind. Pursuant to the San Francisco Fair Chance Ordinance, Ouster considers qualified applicants with arrest and conviction records for employment. If you have a disability or special need that requires accommodation, please let us know.#J-18808-Ljbffr

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