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Senior Principal ASIC Design Engineer (Hybrid)
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$143,000 - $243,100 a year
Full-time
- Our employees work on the world’s most advanced electronics – from saving emissions in the City of Lights to powering the Mars Rover to protecting the F-35 fighter jet.
- We are seeking a very senior level engineer to: Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from concept to production.
- Defining detailed test plan and implementing Verilog simulation testcases to verify design functionality.
- Required Education, Experience, & Skills Proficient in Verilog language for ASIC/FPGA design Knowledge of ASIC and FPGA design flows is highly desirable Knowledge simulation and verification methodologies (VCS simulator, UVM) Proficient in ASIC/FPGA timing closure/area optimization techniques Hands on Experience with bring-up of ASIC/FPGA designs Excellent organization and communication skills for interacting between different design groups Proficiency in C/C
- Preferred Education, Experience, & Skills BS in EE or Computer Science, MS or Doctoral degree preferred 10+ years of experience in ASIC/FPGA Development (Verilog, System Verilog, UVM) Pay Information Full-Time Salary Range: $143000 - $243100 Please note: This range is based on our market pay structures.
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