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Senior Principal ASIC Design Engineer
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$160,000 - $220,000 a year
Full-time
- As a key member of Fortinet's ASIC design team you will help design and architect Fortinet s Next-Generation System-On-Chip FortiASIC to accelerate world's most powerful networking security system.
- Fortinet's SOC ASIC enables FortiGate to achieve best-in-class throughput with consolidated security and networking capabilities.
- You will play a principal role in developing next-gen SOC architecture, perform IP integration, chip level RTL design & verification and lead low power design methodology.
- Candidate must be able to work with self-motivation and deliver on commitments with challenging schedules, lead design teams through various phases of ASIC design process including RTL design, chip level verification, coverage analysis, synthesis and STA. Candidate must possess solid knowledge in SOC design techniques, analog IPs, high speed IO protocols, CPF/UPF power design flow and lint/CDC tools.
- Familiarity with ARM subsystem, SMP multi-socket cache coherency.
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