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Senior FPGA Electrical Engineer
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- Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, create specification documents.
- Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks.
- Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs∯*∯
- 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design.
- Experience in EDA tools such as simulators (e.g., Questa), lint checkers (e.g., Spyglass) synthesis (e.g., Synopsys Synplify), - FPGA tools (e.g., Vivado).
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