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Senior Digital Integration & Timing Engineer
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$150
- This is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
- Knowledge of the entire ASIC design flow from RTL integration through synthesis, static timing analysis, scripting, P&R to tapeout.
- Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues.
- Logic synthesis execution for efficient PPA using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus.
- Familiarity with DFT and backend related methodologies and tools.
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