Onsemi

You will work in a cross-functional team, to drive low-cost test solutions for complex Analog / Mixed Signal ICs, using Advantest and Teradyne ATE platforms.. Define product DfT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitives to wafer-fab process and parametric parameters.. Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window.. During these various stages of Post-Silicon validation, you will interact with various cross-functional teams such as Design, DfT, Design Validation, Program Management, QRE/CQE, and Bench Characterization and Apps development teams

product engineer

This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets. In this role, you’ll be a member of New Product Development team, tasked to work on new product development from design inception to manufacturing release. You will work in a cross-functional team, to drive low-cost test solutions for complex Analog / Mixed Signal ICs, using Advantest and Teradyne ATE platforms. Knowledge and experience with software development using of C++ / C / Python / JAVA is necessary. Candidate should know ATE platform architecture and programming language to develop low level ATE code for Analog / Mix Signal blocks. End goal is to design and productize deep Analog and Mix Signal test automated solutions, enabling organization benchmarks in quality, efficient code, and test-cost goals. As a member of Product & Test Engineering Team, you will own, participate, lead, and drive below activities: Primary responsibilities: Define product DfT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation Post-Si bring-up and validation of all functional and test features. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitives to wafer-fab process and parametric parameters. Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window. Execute qualification cycles for Si and package to automotive, industrial, and commercial standards (as per the primary product market) During these various stages of Post-Silicon validation, you will interact with various cross-functional teams such as Design, DfT, Design Validation, Program Management, QRE/CQE, and Bench Characterization and Apps development teams Will actively own or be part of a team that owns ATE Test Solutions, including HW design, socket design, ATE Resource Allocation, Board Schematic, Layout, and Diagnostic code Will own product from bring-up to RTM (~12-14mo) and also own all the Product Entitlement goals and critical metrics for a successful ramp The candidate, in this role, is expected to lead and assist in defining and writing up test-specs for automation as well as STML (standard test methods library) to be used across multiple ATE tester platforms. Document gaps, lessons learned, and best practices with Design DfT teams to address on future products. #J-18808-Ljbffr

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