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Principal ASIC RTL Designer
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Full-time
- As Principal Engineer (ASIC / SoC), you will be the leading ORAN SoC design and collaborate with Firmware & design team for product requirement definition, micro architecture.
- This role is an excellent opportunity for engineers with 12+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting 5G / NTN product market space.
- RTL coding & simulation in Verilog/SystemVerilog/VHDL
- Design simulation & checking with Cadence front end tools: Xcelium, SimVision, Jasper RTL Apps
- Front end digital design and implementation – RTL coding, CDC, Lint, and synthesis
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