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Physical Design Engineer Intern
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Full-time
- The Physical Design intern will support the physical design team with all aspects of physical design implementation and verification of Ambarella's cutting edge SoC for sub-28nm technology node.
- The Physical Design Intern will support the following areas within the physical design team; floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.
- Good understanding in VLSI digital design/Layout/Timing closure
- Basic knowledge on circuit design, device delays, and timing at gate-level
- Familiar with industry EDA tools such as Cadence SoC Encounter, Synopsys ICC/Primetime, Magma Talus/Blast, and Mentor Calibre.
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