Upvote
Downvote
Design Verification Engineer
Share Job
- Suggest Revision
- The purpose of this job is to help guarantee specification compliancy of the digital design by means of verification methodology and concepts.
- Support verification strategy for digital and mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM.
- Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.
- The ideal candidate has an experience of 5+ years in state-of-the art verification methodologies related to the verification of SoCs · Fluent in System Verilog RTL coding and ASIC design methodology · System Verilog for verification using advanced verification methodologies (preferably UVM or similar such as Specman-e, OVM, SystemC, etc.)
- Fluent in simulation and regressions tools e.g., Cadence Incisive, vManager, IMC
Active Job
Updated 14 days agoSimilar Job
Relevance
Active