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Design Lead RTL - DDR IP (Einfochips)
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Full-time
- Description :What You'll Be Doing: Lead the development of custom radiation hardened DDR3 IP, controller, and PHY.Serve as a point of contact for internal and external DDR IP development-related activities.
- Oversee work on logic design, Clock Domain Crossing (CDC) solutions, and voltage plane optimization.
- Oversee verification processes for DDR IP developmentCandidate will be using: RTL CompilerDesign CompilerASIC synthesis tools like DC, GenusFPGA tool platformCDC toolsWhat We Are Looking For: 5+ Years of experience in ASIC DesignExperience in DDR IP developmentFamiliarity with logic design, CDC solutions, and voltage plane optimization.
- Familiarity with analog circuit development, with a focus on IO circuitry and PHY development.
- Strategic awareness of the competitive landscape for DDR IP.Excellent communication and teamwork skills.
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