Acara Solutions

We have a remote, hybrid, or onsite contract position (6+ months expected) at our Semiconductor client for an ASIC Developer with Cadence Tempus experience.. Your primary responsibility will be to verify ASIC implementations for timing and ASIC Design Audits (Lint, CDC, DFT, etc.). General ASIC developmentParticipate in the RTL implementation, synthesis, formality check as well as ECOsSupport post-layout timing closure and verificationDetailed ASIC Back-End DevelopmentSupport the design team to develop Block / Full Chip Level Constraints, verify timing constraints with industry standard tools and run synthesis.. Job Requirements Required Skills / Qualifications:Bachelors/Master's in electrical engineering, Computer Engineering or Computer ScienceMin 10 years of proven silicon design experience in ASIC ImplementationMin 5 years of experience in RTL design, design verification, synthesis (and highly desired Genus experience (next-generation RTL synthesis and physical synthesis tool. formal verificationMin 2 years of experience in Tempus and Verilog simulation toolsMin 2 years of experience in LINT, CDC, and RDC (SpyGlass experience strongly preferred )Preferred Skills / Qualifications:FPGA and ASIC System On Chip Design Experience

semiconductor

Description Acara Solutions has been providing engineering talent nationally to advanced manufacturing firms for 65 years. We have a remote, hybrid, or onsite contract position (6+ months expected) at our Semiconductor client for an ASIC Developer with Cadence Tempus experience. The contractor can choose to work from home anywhere in the U.S. or from the company's San Jose, CA or Allentown, PA offices (with a preference of hybrid at these two locations). Estimated hourly rate: $110.Cadence Tempus experience is required in addition to RTL design & verification, and Genus is highly desired. Your primary responsibility will be to verify ASIC implementations for timing and ASIC Design Audits (Lint, CDC, DFT, etc.) at the block and full chip level.General ASIC developmentParticipate in the RTL implementation, synthesis, formality check as well as ECOsSupport post-layout timing closure and verificationDetailed ASIC Back-End DevelopmentSupport the design team to develop Block / Full Chip Level Constraints, verify timing constraints with industry standard tools and run synthesis.Support LINT, clock-domain crossing, and reset-domain-crossing analysis.Perform Static Timing Analysis both pre-layout and post-layout.Support any Timing of Functional ECOs as needed. Job Requirements Required Skills / Qualifications:Bachelors/Master's in electrical engineering, Computer Engineering or Computer ScienceMin 10 years of proven silicon design experience in ASIC ImplementationMin 5 years of experience in RTL design, design verification, synthesis (and highly desired Genus experience (next-generation RTL synthesis and physical synthesis tool)) & formal verificationMin 2 years of experience in Tempus and Verilog simulation toolsMin 2 years of experience in LINT, CDC, and RDC (SpyGlass experience strongly preferred )Preferred Skills / Qualifications:FPGA and ASIC System On Chip Design Experience

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