Upvote
Downvote
Senior Application Support Engineer (UVM, System Verilog, VHDL)
Share Job
- Suggest Revision
- Minimum of 2+ years of Digital Design/Verification experience
- Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design
- Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies
- Knowledge of UVM and System Verilog for Verification
- Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators
Expired 8 days agoInactive Job
Similar Job
Relevance
Active