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Experience designing, testing, and integrating digital, mixed signal, and electrical system interconnect. Experience using schematic capture tools and interpreting schematics and/or performing advanced FPGA firmware development (VHDL or Verilog.
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Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunitiesSolve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
$356,500Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Areas of expertise include electrical interconnect, mechanical, pneumatic, fluid flow, or vacuum technologies. Follows work orders, schematics, wiring diagrams, engineering specifications, sketches, assembly shop and production operations sheets, parts and wire lists, written and/or verbal instructions to construct electro-mechanical, vacuum and/or pneumatic assemblies, subassemblies and components.
$26.4 an hourFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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We are seeking an energetic and highly motivated SoC performance engineer to drive development of our on-chip communication interconnect and memory Quality-of-Service features. simulator for iPhone/iPad/Mac/Watch SoCs. You will model new, emerging workloads such as Augmented Reality (AR) and Machine Learning (ML.
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The RoleThis role is for anyone of our US locations (Santa Clara, CA., Portland, OR., Raleigh, NC, or remote US)As a Senior Principal Cache Coherency Subsystem Verification Engineer, you will the opportunity to work on and lead the verification of a server-class microprocessor-based Coherent Mesh interconnect subsystem.
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You drive high-level performance analysis on complex workloads, with the goal to optimize the GPU with rest of the Memory System IP (Interconnect, Last-level Cache, Memory Controller). Our GPU Architect team delivers whole system architecture-level design for Samsung’s current and next-generation mobile GPU. Depending on the functional discipline, they’re responsible for anywhere from early-stage architectural exploration, research work focusing on graphic and machine learning, defining new features, modeling, to diving into microarchitecture design and programming work.
$257,336 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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5+ years work experience in microprocessor, SoC, memory controller and/or interconnect IP design. As an RTL Design Engineer, you would responsible for one or more functional units of the Memory Controller while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.
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This is an Engineering position for High Speed Interconnect Products (HSIP). Experience with digital signal processing. Digital signal processing knowledge. A Bachelor's Degree in Electrical and Electronic Engineering or Computer Science with 8+ years relevant industry experience or a Masters degree in Electrical and Electronic Engineering or Computer Science with 6+ years relevant industry experience.
$190,000 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Route, fasten and interconnect components (i.e. resistors, diodes, capacitors, transistors) to specified contact points following wiring diagrams to form circuit wiring. Route, fasten and interconnect components (i.e. resistors, diodes, capacitors, transistors) to specified contact points following wiring diagrams to form circuit wiring.
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Understanding of fabric interconnect protocols like ARM AXI and CHI. Define memory subsystem requirements, including Power, Performance, Area (PPA), Reliability, Availability, Serviceability (RAS), Quality of Service (QoS), Security, and Debug.
$200,000 a yearFull-timeExpandApply NowActive JobUpdated 29 days ago - UpvoteDownvoteShare Job
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As fabric architect, you will be responsible for the internal interconnect architecture specification and its performance, power, area requirements. Thorough knowledge of large scale on-chip fabric or on-chip interconnect architecture.
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Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
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Experience helping customers build and deploy hardware in cloud covering rack-scale architecture, accelerator/IO interconnect, power efficiency and cooling solutions etc. Support Product Managers on defining IP, interconnect, CSS designs for next-gen hardware.
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You will be part of an R&D team developing high speed analog and mixed-signal integrated circuits for DDR/LPDDR PHY, High Bandwidth Memory (HBM) PHY, Universal Chiplet Interconnect Express (UCIe) PHY, and Mobile Storage PHY IPs. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team.
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Knowledge and experience with Interconnect protocols like AXI/ACE/OCP/CHI. Exposure to various ASIC design verification tools with good digital design concepts. Support for prototyping in FPGA and/or Emulation.
$230,000 a yearFull-timeExpandApply NowActive JobUpdated 9 days ago
interconnect job in Austin, TX
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