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Required Education In accordance with Southern Association of College and Schools Commission on Colleges (SACSCOC) requirements: Bachelor's or Associate's degree in Art, Graphic Design, Commercial Art, Computer Graphics, Graphic Design, Printing/Production, or Visual Communication.
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Design experience should include ASIC design using industry-standard hardware description languages (Verilog)? Assist customers with adopting Cadence Front End tools in Synthesis with Genus DFT & Scan with Encounter Test (ET) by providing methodology and tool knowledge to IC design process, validated through successful design tapeouts.
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A degree(s) in cartography, geography, graphic arts or relevant field may be substituted per LCRA guidelines for certain years of experience. - Skill in computer graphic production including, but not limited to vector and raster images for prepress, computer terminal display and offset printing.
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Services may include traffic signal design, ITS design, signal timing analyses, illumination/lighting, ADA/sidewalk design, signing, and pavement marking and design. Experience in traffic engineering including traffic signal design and timing, operational analysis, and capacity analysis.
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For EIT – Assist in generating project deliverables, including plan design and production, specifications and other assigned tasks for water / wastewater treatment systems. Minimum 1 year of experience in municipal water / wastewater design for EIT role, 5 years for the PE role; experience in drainage design is a big plus.
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Knowledge of basic analog blocks: Linear and Switching voltage regulators, DAC, ADC, comparators, oscillators, high speed clock circuits Strong knowledge in Matlab, Verilog-A, Verilog and SystemVerilog Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF Good experience in Synopsys based mixed-signal co-simulation flow Scripting: C, python, perl, csh.
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Preferred Qualifications: Certificate or graduate work in educational technology, instructional design, or learning science is a plus. Understand and communicate best practices in the design, interdependencies, and implementation of digital content and digital functionality to the project teams, vendors, and authors.
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Maintains, tests, troubleshoots, repairs and calibrates video graphic displays and video display terminals, printed circuit boards, printers and two-way radio communications systems. The Transportation Security Administration (TSdivision of the USA Dept. of Homeland Security) requires all employees of the Austin-Bergstrom International Airport to pass a minimum 10-year criminal background investigation and security threat assessment.
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About Toole Design Toole Design is the leading engineering, planning, and landscape architecture firm specializing in multimodal transportation. Since 2017, a team of Toole Design engineers have provided full-time, on-site staff augmentation to the City of Austin's Transportation and Public Works Department to deliver Mobility Bond projects focusing on bikeway, pedestrian, and transit related infrastructure.
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As the Mechanical BIM Manager, you will lead a highly creative and efficient Mechanical BIM team, tasked with managing the design of challenging and complex projects with innovative solutions for Amazon owned Data Center facilities.
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Halff has immediate openings for a Senior Project Manager /Senior Design Engineer in our Austin Transportation Practice. Experience should include leading roadway design projects, coordinating with clients and leading delivery of transportation design projects for DOT.
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Senior Network Developer (Hyperscale Network Design)Location: United StatesSupports the design, deployment, and operations of a large-scale global Oracle cloud computing environment (Oracle Cloud Infrastructure - OCI.
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Bachelor's degree in Planning, Landscape Architecture, Urban Design, Engineering, Geology, Biology, Environmental Science, Anthropology, Archaeology, or related field and 10 years relevant experience.
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Design knowledge of high-speed I/O SerDes architectures and blocks, plus general mixed-signal IP, e.g. CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO, etc. Provide expertise in translating post-silicon learnings into suggestions for the new IP design process for SerDes IP. PREFERRED EXPERIENCE: 10-15 years of professional experience in the semiconductor industry doing analog mixed-signal circuit/system design, analysis, validation and/or test, characterization and debug.
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Overview As a Water Resources Engineer for CEC, you will perform hydrologic and hydraulic analysis, dam safety assessment, design, compliance, and rehabilitation, water resource utility infrastructure and stormwater facilities design, stream restoration design, and conduct floodplain and drainage studies.
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graphic design jobs Company: Agreeya Solutions in Austin, ID, Nebraska
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