Lead CAD Tool Optimisation Engineer (RTL Simulations)

Apple Inc. is looking for an experienced CAD engineer to join their CAD Hardware Tech team in Cambridge, Massachusetts. This role involves optimizing the simulation tools used in chip design and collaborating with internal and vendor teams on new methodologies. The ideal candidate holds a BS, MS, or PhD in a relevant field with a minimum of 5 years of experience in RTL simulation tools. Preferred skills include knowledge of the Cadence tool chain and familiarity with SystemVerilog, Verilog, or VHDL. #J-18808-Ljbffr