CAD Tools Optimisation Engineer (Design Verification)

The role is part of Apple’s CAD Hardware Tech team, responsible for automating processes in designing Apple’s chips used across devices. You will collaborate with both vendor and internal teams to develop and deploy new methodologies that optimize simulation tools, enhance performance, and reduce resource requirements on large‑scale simulations. Description As an experienced CAD engineer, you will assist with delivering high quality infrastructure for automating chip design processes. Specifically, as chip designs become larger, there is a growing need to optimize the performance of simulation tools to maximize efficiency and reduce compute time and memory usage. The scope of work includes developing and deploying new methodologies, supporting and debugging issues on large‑scale simulations, and working closely with cross‑functional teams. Minimum Qualifications BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering, or a related field Minimum 5 years of experience working on RTL simulation tools Strong foundation on Linux and grid computing systems Knowledge of scripting languages such as Python or Perl Strong interpersonal and analytical skills Ability to work well within a team and be productive under tight schedules Fluency in English Preferred Qualifications Expert knowledge of the Cadence tool chain Familiarity with SystemVerilog, Verilog, or VHDL A curiosity about GPU, PMU, CPU, SOC architecture, and micro‑architecture Apple is committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make reasonable accommodations. Apple will consider all qualified applicants with criminal backgrounds in a manner consistent with applicable law. #J-18808-Ljbffr