Senior Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.The GPU Design Verification Engineer - Shader Core will focus on planning, building and executing the verification of new and existing features for AMD's shader processor core which is used in the GPU, resulting in no bugs in the final design.THE PERSON:You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Exposure to leadership or mentorship is an asset.KEY RESPONSIBILITIES:Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verifiedBuild test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use casesEstimate the time required to write the new feature tests and any required changes to the test environmentBuild the directed and random verification testsDebug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issuesReview functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirementsPREFERRED EXPERIENCE:Proficient in IP level ASIC verificationProficient in debugging firmware and RTL code using simulation toolsProficient in using UVM testbenches and working in Linux and Windows environmentsExperienced with Verilog, System Verilog, C, and C++Graphics pipeline knowledgeDeveloping UVM based verification frameworks and testbenches, processes and flowsAutomating workflows in a distributed compute environment.Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/processStrong background in the C++ language, preferably on Linux with exposure to Windows platformGood understanding and hands-on experience in the UVM concepts and SystemVerilog languageGood working knowledge of SystemC and TLM with some related experience.Scripting language experience: Perl, Ruby, Makefile, shell preferred.ACADEMIC CREDENTIALS:* Undergrad degree required. Bachelors or Masters degree in computer engineering/Electrical Engineering preferred.This role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.This posting is for an existing vacancy.