R&D Engineering, Sr Architect

Date posted 05/19/2026Category Engineering Hire Type Employee Job ID 17217 Base Salary Range $226000-$338000 Remote Eligible No Date Posted 05/19/2026We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years building EDA software that has to hold up under real-world custom IC design pressure, the kind where a layout decision at 3nm can make or break a tape-out schedule. You know that the difference between a tool designers trust and one they route around is usually in the details, the algorithm that shaves two hours off a placement run, the infrastructure decision that makes GAA process nodes actually usable instead of theoretically possible.You think in systems, not just features. When someone asks for a new routing capability, you are already mapping the impact on existing flows, the training burden on designers, and the maintenance cost three releases from now. You have used Custom Compiler or Virtuoso enough to know where the pain points live, and you care about solving them at the architecture level, not patching them at the UI level.You are comfortable setting direction for junior engineers while still writing code yourself. You do not need a perfect spec to get started. You talk to IP teams, understand what 2nm and 14A nodes actually demand, and build tools that make their jobs easier. At Synopsys, you will work on the platform that powers custom IC design across the industry, and what you architect will ship to customers building the next generation of chips.What You'll Be DoingArchitect and develop placement and routing infrastructure for Custom Compiler targeting advanced GAA and FinFET process nodes including 5nm, 3nm, 2nm, and 14ADesign and implement layout automation features that directly improve designer productivity in circuit layout for cutting-edge process technologiesSet technical direction and operational specifications for Custom Compiler software based on analysis of customer workflows and EDA ecosystem requirementsDrive research and development of new algorithms and tools that address real bottlenecks in custom IC layout for advanced nodesCollaborate with Synopsys IP teams to integrate and proliferate Custom Compiler layout automation technologies across internal design flowsMentor and guide junior engineers on software architecture, coding standards, and quality practices specific to EDA tool developmentManage maintenance and evolution of existing tool sets and infrastructure across product releases, balancing new feature development with stabilityThe Impact You Will HaveEnable designers to complete complex custom IC layouts for 3nm and below process nodes faster and with fewer iterationsReduce time-to-tapeout for Synopsys IP teams and external customers through smarter placement and routing automationShape the technical roadmap for Custom Compiler, influencing how thousands of analog and custom designers work dailyAccelerate adoption of advanced GAA and FinFET technologies by making them accessible through better EDA toolingBuild infrastructure that scales across multiple process nodes and design styles, creating leverage for the entire Custom Compiler platformImprove designer productivity measurably through tools that handle the complexity of 2nm and 14A node constraintsStrengthen Synopsys' position in the custom design EDA market by delivering capabilities competitors cannot matchWhat You'll NeedBachelor's degree with a minimum of 15 years of related experience, or an advanced degree with a minimum of 13 years of related experience, in building EDA tools, with a deep focus on custom IC design automation.Hands-on experience with Custom Design platforms, specifically Synopsys Custom Compiler or Cadence Virtuoso, in a development or power-user capacityStrong expertise in placement and routing algorithms for analog, mixed-signal, or custom digital layoutsProven ability to architect software systems that balance performance, maintainability, and extensibility in complex EDA environmentsDirect experience working with advanced process nodes (7nm or below), understanding the layout constraints and design rules that matter at scaleBachelor's or Master's in Computer Science, Electrical Engineering, or equivalent with demonstrable EDA software architecture experienceExperience working with semiconductor IP teams or custom IC design teams is a strong plusWho You AreYou can explain a complex routing algorithm tradeoff to an IP designer in two sentences without losing the technical nuanceYou write code that other engineers can actually maintain, and you care about that as much as you care about the feature itselfYou push back when a feature request does not align with the architecture, and you do it with a better alternative in handYou are comfortable presenting technical direction to senior leadership and defending your choices with data, not just intuitionYou move between deep technical work and cross-functional collaboration without losing momentum, whether that is debugging a placement engine or aligning roadmaps with the IP teamYou treat maintenance and infrastructure work as seriously as new feature development because you know that is what keeps a platform aliveThe Team You'll Be Part OfYour recruiter will share more about the team structure and mission during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.#TPGAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.