Design Verification Engineer

Help Verify the Silicon Behind Next-Generation Interconnect TechnologyWe are partnering with an advanced semiconductor innovation team focused on next-generation high-speed interconnect technologies, AI infrastructure, and future compute architectures. They are seeking a senior-level Design Verification Engineer to take full ownership of pre-silicon functional verification for a cutting-edge mixed-signal PHY test chip through tape-out sign-off.This is not a support role or traditional staff augmentation engagement. This is an opportunity for an experienced DV engineer to lead verification strategy, infrastructure, and coverage closure within a lean, technically elite engineering environment where your expertise directly impacts silicon success.The project centers on a 36 I/O full-duplex die-to-die interconnect PHY characterization chip designed to validate novel signaling architectures and generate silicon data that will help shape future interconnect scaling strategies.You’ll work closely with digital chip leadership, highly respected analog designers, and senior lab engineering experts on a focused tape-out mission with meaningful technical depth and clear ownership.Job Title: Design Verification EngineerLocation:Minneapolis, MNWhat You’ll Be DoingYou will own the complete functional verification effort for the test chip, including: Developing and maintaining the full-chip DV plan Building UVM/SystemVerilog verification environments from scratch Implementing coverage-driven verification methodologies Creating assertions and formal verification checks Managing regressions and debugging failures Driving coverage closure and sign-off readiness Supporting post-silicon bring-up with debug collateral and waveform analysis Documenting methodology, coverage, and verification decisions Key Verification Areas Include Internal eye monitor logic PRBS-based error counting functionality I2C management and CSR verification Top-level integration and reset sequencing Multi-lane characterization control logic This is a technically rich mixed-signal verification environment involving custom analog control boundaries, behavioral modeling, and complex integration challenges that go well beyond standard block-level DV work.Required ExperienceWhat We’re Looking For BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field 6+ years of functional verification experience in UVM/SystemVerilog environments Experience serving as primary or lead DV engineer on at least one complete tape-out Strong experience building UVM environments from the ground up Expertise in: Functional coverage modeling Coverage-driven verification Regression management RTL and waveform debugging Assertion-based verification Experience verifying serial management interfaces such as: I2C SPI APB AHB Strong problem-solving and debugging capabilities Ability to work independently in a lean, fast-moving environment Preferred Experience Formal verification experience using JasperGold, VC Formal, or similar tools Mixed-signal or PHY verification experience Real-number modeling (RNM) or Verilog-AMS familiarity PRBS pattern generation and error detection verification experience Post-silicon validation or lab bring-up support experience Experience correlating simulation and silicon behavior Startup or contractor environment experience The Type Of Engineer Who Thrives HereThis role is ideal for someone who: Enjoys broad ownership and accountability Proactively identifies coverage gaps before sign-off Likes solving difficult verification and debug challenges Adapts methodology creatively in mixed-signal environments Communicates effectively across engineering disciplines Thrives in small, highly collaborative teams Finds tape-out execution energizing rather than stressful You’ll have direct influence over verification strategy, sign-off criteria, and the overall success of the silicon program.Why Engineers Are Interested in This Opportunity Full ownership of the DV function from day one Opportunity to build verification infrastructure from scratch Technically interesting analog/digital verification challenges Direct collaboration with world-class analog and lab engineering teams Lean environment with fast decision-making and visible impact Opportunity to contribute to future interconnect and AI infrastructure technologies Defined timeline and clear deliverables ideal for experienced contractors If you’re a senior Design Verification Engineer who enjoys owning verification challenges end-to-end and wants to contribute to advanced silicon development in a high-accountability environment, we’d love to connect with you. Upon Completion Of Waiting Period, Consultants Are Eligible ForMedical and Prescription Drug Plans Dental Plan Vision Plan Health Savings Account Health Flexible Spending Account Dependent Care Flexible Spending Account Supplemental Life Insurance Short Term and Long Term Disability Insurance Business Travel Insurance 401(k), Plus Match Weekly Pay About ManpowerGroup, Parent Company of: Manpower, Experis, Talent Solutions, and Jefferson Wells. ManpowerGroup® (NYSE: MAN), the leading global workforce solutions company, helps organizations transform in a fast-changing world of work by sourcing, assessing, developing, and managing the talent that enables them to win. We develop innovative solutions for hundreds of thousands of organizations every year, providing them with skilled talent while finding meaningful, sustainable employment for millions of people across a wide range of industries and skills. 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