Design Verification Engineer

Title: Design Verification EngineerLocation: Minneapolis, MN Duration: 9 Months Compensation: $55-$62/hr Description:We are seeking an experienced contract Design Verification (DV) Engineer to take full ownership of verification for a high-speed interface test chip, operating in a lean, high-impact environment with a clear focus on pre-silicon coverage closure and tape-out sign-off. This role is responsible for developing and executing the full-chip DV plan, defining coverage goals, and building robust UVM/SystemVerilog test environments across key blocks including PRBS error counting, eye monitor control, PHY configuration, and top-level integration. The engineer will implement assertion-based and formal verification methodologies, manage regression infrastructure, and drive issue triage and resolution in close collaboration with RTL and design teams. Additionally, this role supports post-silicon bring-up by providing debug artifacts and test vectors, while maintaining thorough documentation of verification plans, coverage closure, and methodologies. Success in this role requires a strong ownership mindset—proactively identifying coverage gaps, adapting verification strategies to complex mixed-signal boundaries, and ensuring all work is clearly documented to enable seamless knowledge transfer at the end of the engagement. Required Skills and Experience: Bachelor’s, Master’s, or PhD in Electrical or Computer Engineering (or related field)6–12 years of verification experience with at least one full tape-out as a lead or primary DV engineerStrong hands-on experience building UVM/SystemVerilog testbenches from scratchExperience verifying standard interfaces (I2C, SPI, APB, AHB, etc.)Solid coverage-driven verification experience (functional + code coverage, closure)Strong debugging skills across RTL and simulation environmentsAble to ramp quickly and deliver within a fixed, tape-out-driven timelineComfortable working in a small, high-ownership team environment\Preferred Skills and Experience: Experience with formal verification tools (JasperGold, VC Formal, etc.)Familiarity with PHY modeling or mixed-signal simulation environmentsExperience with real-number modeling (RNM) or Verilog-AMSUnderstanding of PRBS patterns and error-checking logicPost-silicon bring-up or lab support experienceExperience with ATE vectors or simulation-to-silicon correlationPrior contract or startup experience